1. Technical Field
The present disclosure relates to semiconductor memories, and to a technology to solve performance degradation of a memory device caused by different performance of memory functions depending on a position of a memory cell.
2. Description of the Related Art
Semiconductor memories are used for devices such as embedded devices, computers, and information and communications devices. In recent years, technologies to implement large capacity, small size, high-speed rewriting, high-speed reading, and low power consumption operations have been intensively developed.
In particular, a Resistive Random Access Memory (ReRAM) that uses a resistance change element for a storage element has a feature of high-speed, low-power-consumption rewriting capability as compared with conventional flash memories.
The resistance change element refers to an element having a property in which resistance reversibly changes in response to an electrical signal, and having capability of nonvolatily storing data corresponding to this resistance.
As a nonvolatile semiconductor storage device using the resistance change element, a generally known nonvolatile semiconductor storage device includes an array of memory cells, called so-called 1T1R type, arranged in a matrix at positions of intersection points of bit lines, word lines, and source lines which are orthogonally arranged, each of the memory cells being formed by connecting the resistance change element with a metal oxide semiconductor (MOS) transistor in series.
PTL 1 describes a nonvolatile semiconductor storage device including 1T1R type memory cells.
FIG. 1 is an equivalent circuit diagram of the memory cell described in PTL 1.
In FIG. 1, resistance change element 101 is electrically connected to cell transistor 102 including an N-channel metal oxide semiconductor (NMOS) transistor.
Information stored in the memory cell is recorded as magnitude of resistance of resistance change element 101.
For example, the stored information is read by applying 0 V to source terminal 103, by applying a positive voltage to gate terminal 104, by applying a positive voltage to bit terminal 106, by applying 0 V to ground terminal 107, and by detecting magnitude of a current value that flows from bit terminal 106 to source terminal 103.
Rewriting of information is performed as follows.
An operation to change resistance change element 101 from a state where the resistance is high (a high resistance state) to a state where the resistance is low (a low resistance state) is as follows.
A voltage of 0 V is applied to bit terminal 106 and ground terminal 107, a positive voltage is applied to gate terminal 104, and positive voltage pulses are applied to source terminal 103. This operation causes resistance change element 101 to transition from the high resistance state to the low resistance state.
An operation to change resistance change element 101 from the low resistance state to the high resistance state is as follows.
A voltage of 0 V is applied to source terminal 103 and ground terminal 107, a positive voltage is applied to gate terminal 104, and positive voltage pulses are applied to bit terminal 106. This operation causes resistance change element 101 to transition from the low resistance state to the high resistance state.
FIG. 2 is a diagram illustrating a change in a potential difference across the resistance change element and in a source-drain potential difference of the cell transistor over time, when the memory cell using the resistance change element described in PTL 1 transitions from the high resistance state to the low resistance state. FIG. 3 is a diagram illustrating a relationship between a voltage and a current of the resistance change element and the cell transistor, when the memory cell using the resistance change element described in PTL 1 transitions from the high resistance state to the low resistance state. With reference to FIG. 2 and FIG. 3, a detailed description will be given about the change in the voltage and the current of resistance change element 101 and cell transistor 102 when resistance change element 101 is changed from the high resistance state to the low resistance state.
In FIG. 2, reference numeral 202 illustrates the change in the potential difference across resistance change element 101 over time, and reference numeral 201 illustrates the change in the source-drain potential difference of cell transistor 102 over time, when positive voltage V1 is applied to bit terminal 106 in the high resistance state. Immediately after positive voltage V1 is applied to bit terminal 106, the potential difference applied across resistance change element 101 is VH, and the source-drain potential difference of cell transistor 102 is V1−VH.
From this state, the resistance of resistance change element 101 starts to change at time T1 at which the transition starts, and then resistance change element 101 transitions to the low resistance state at time T2. After the transition to the low resistance state, the potential difference applied across resistance change element 101 becomes VL, and the source-drain potential difference of cell transistor 102 becomes V1−VL. At this time, VL<VH.
FIG. 3 illustrates the change in the current value when resistance change element 101 transitions from the high resistance state to the low resistance state. Reference numeral 301 illustrates a relationship between the source-drain voltage (horizontal axis) and the current that flows between the source and drain (vertical axis) of cell transistor 102 when the voltage at the gate terminal of cell transistor 102 is V1−VH. When resistance change element 101 is in the high resistance state, the source-drain voltage difference is V1−VH, and thus the current that flows between the source and drain is the current value at point 303 on line 301. Reference numeral 302 illustrates a relationship between the source-drain voltage and the current that flows between the source and drain of cell transistor 102 when the voltage at the gate terminal is V1−VL. After the transition to the low resistance state, the source-drain voltage difference is V1−VL, and thus the current that flows between the source and drain is the current value at point 304 on line 302.
PTL 2 describes a technology to prevent degradation in performance of a memory device caused by performance of memory functions different depending on a position of a memory cell array.
FIG. 4 illustrates a structure described in PTL 2. FIG. 4 illustrates a stacked layer structure stacked on a semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . , an n-th conductive line, an n-th variable resistance element, and a (n+1)-th conductive line, where n is a natural number equal to or larger than 2. The stacked layer structure further includes a first to a (n+1)-th drivers Dr1(1), Dr2(1) that drive the first to (n+1)-th conductive lines L1(1), L2(1), . . . , L(n+1)(1). Sizes of the first to (n+1)-th drivers Dr1(1), Dr2(1) become gradually larger from the first driver to the (n+1)-th driver.
When a plurality of memory cell arrays are stacked, a time constant of a via plug for connecting a conductive line in each of the memory cell arrays and the driver for driving the conductive line differs from one memory cell array to another. However, by minimizing increase in a region in which the drivers are formed with the above-described structure for increase in a number of memory cell arrays to be stacked, an advantage of large capacity due to three-dimension of the memory cell arrays can be obtained.
PTL 3 provides, in a bank scheme ROM, a technology to reduce variations in bit line potential caused by a difference in a position within a bank of a selected memory cell, and to achieve increase in margin of reading. The ROM of PTL 3 includes: a memory cell array including memory cells arranged in a matrix, each of the memory cells including a memory transistor; first and second main bit lines which are each provided with predetermined potential for reading information from the selected memory cell; and a plurality of first and second sub bit lines which are provided for each column of the memory cells and serve as a common source and a common drain of the memory transistor that constitutes the memory cell. Moreover, the ROM includes: a plurality of word lines provided for each row of the memory cells, each of the word lines being connected to gates of the memory transistors forming the memory cells; a first bank selection transistor connected between the first sub bit line and the first main bit line for selecting the memory cell column; and a second bank selection transistor connected between the second sub bit line and the second main bit line for selecting the memory cell column. Moreover, the ROM includes bank selection lines provided for each of the bank selection transistors and connected to each gate. Potential according to a position of the selected word line in the memory cell array is applied to each bank selection line as on potential of the bank selection transistor.